Jakub Szefer
Associate Professor
Dept. of Electrical and Computer Engineering
Northwestern University
(starting Jan. 2025)
Address: Technological Institute, 2145 Sheridan Road, Evanston, IL 60208, USA
E-mail: jakub.szefer@northwestern.edu

Prospective students interested in Ph.D. study with our group should apply directly to the graduate school and list my name as a potential adviser so I can find the application more easily. Applications are reviewed in December of each year.

I am available for cybersecurity consulting work with companies and other organizations, please connect with me via LinkedIn if you are looking for cybersecurity consulting assistance.

Current Ph.D. students:
• Yizhuo Tan
• Theodoros Trochatos
• Anthony Etim
• Sanjay Deshpande
• Chuanqi Xu
• Ferhat Erata

Former Ph.D. students:
• Shanquan Tian, Ph.D. 2023 (Google)
• Shuwen Deng, Ph.D. 2022 (Faculty, Tsinghua University)
• Wen Wang, Ph.D. 2021 (Intel)
• Wenjie Xiong, Ph.D. 2020 (Faculty, Virginia Tech)

ABOUT

I have recently accepted a new faculty position at Northwestern University! Please contact me at my new email address, which is already active. I will officially start at Northwestern University in January 2025.

I am the director of the Computer Architecture and Security Laboratory (CASLAB) where I am fortunate to work with a great group of students. Together, our research broadly focuses on computer security, with special interest in architectures and hardware for securing computer systems: from classical CPUs, GPUs, and FPGAs, to the nascent Quantum Computing systems. Beyond research, I enjoy teaching and have previously received the 2021 Ackerman Award for Teaching and Mentoring when I was working at Yale University.

RESEARCH

My recent, novel research findings include power side-channel vulnerabilities in quantum computer controllers and attacks on reset gates in quantum computers. My other exciting research findings include novel Secure TLBs and frameworks for security verification of processor caches and whole architectures; hardware accelerators for code-based and hash-based post-quantum cryptographic algorithms, as well as hardware accelerators for digital signature schemes currently being considered for standardization by NIST. I also research security attacks and defenses for nascent Cloud FPGA computing paradigm and novel side and covert channels in Cloud FPGAs; and DRAM-based Physically Uncloneable Functions.

My research is supported through current grants: NSF grant 2312754 (Quantum Databases); NSF grant 2245344 (Side Channel Detection and Repair); NSF grant 1901901 (Cloud FPGA Security); and NSF grant 1651945 (DRAM PUFs). In addition, my research benefits from grants and funding from SRC and TII. I am also thankful for industry donations from Xilinx and Intel (formerly Altera), and for donation of cloud computing credits from Amazon (AWS). I am further thankful for support of IBM Quantum and Quantinuum with their in-kind donation of compute access to their quantum computers.

INDUSTRY AND GOVERMENT COLLABORATIONS

I have a new (2023) collaboration with Quantinuum on security of ion-trap quantum computers. I have a new (2023) collaboration with SandboxAQ on hardware implementation of post-quantum cryptographic digital signature schemes. I also have ongoing (since 2020) collaboration and research grant with TII on hardware implementation of post-quantum cryptographic algorithms.

I am a member of ATARC (Advanced Technology Academic Research Center) Global Quantum Working Group. I am also part of the Classic McEliece team in NIST's PQC standardization process.

PROFESSIONAL AFFILIATIONS AND MEMBERSHIPS

I was previously affiliated with Yale's Applied Cryptography Laboratory and Yale's Computers Systems Laboratory, and I had a courtesy appointment in Yale's Computer Science Department.

I am a Senior Member of the IEEE (2019), a Senior Member of the ACM (2022), a Member of the IACR, and an Associate Member of HiPEAC.

RECENT SELECTED PUBLICATIONS

Google Scholar: Citations: 4203, H-index: 34 ⬞ DBLP ⬞ ORCID
Citation data was updated on 2024-07-29.

CASLAB publications page has the full list of our publications.

Chuanqi Xu, Ferhat Erata, and Jakub Szefer, "Exploration of Power Side-Channel Vulnerabilities in Quantum Computer Controllers", in Proceedings of the Conference on Computer and Communications Security (CCS), November 2023.
[ PDF ]  [ BibTeX ] 

Florian Frank, Wenjie Xiong, Nikolaos Anagnostopoulos, André Schaller, Tolga Arul, Farinaz Koushanfar, Stefan Katzenbeisser, Ulrich Rührmair, and Jakub Szefer, "Abusing Commodity DRAMs in IoT Devices to Remotely Spy on Temperature", in IEEE Transactions on Information Forensics and Security, 2023.
[ PDF ]  [ BibTeX ] 

Sanjay Deshpande, Chuanqi Xu, Mamuri Nawan, Kashif Nawaz, and Jakub Szefer, "Fast and Efficient Hardware Implementation of HQC", in Proceedings of the Selected Areas in Cryptography (SAC), August 2023.
[ PDF ]  [ BibTeX ] 

BOOKS

I am an editor of a first book focusing on security of cloud-based FPGAs (Field Programmable Gate Arrays). The book contains 11 chapters contributed by our group and various other researchers.

Jakub Szefer and Russell Tessier, "Security of FPGA-Accelerated Cloud Computing Environments", Sprigner, expected winter 2023.

I am an author of a first book focusing specifically on design of secure processor architectures, including topics such as Trusted Execution Environments and side-channel threats and protections.

Jakub Szefer, "Principles of Secure Processor Architecture Design", Morgan & Claypool Publishers, October 2018.

SEMINARS and TALKS

My recent seminars or invited talks include:

TUTORIALS, SUMMER SCHOOLS, and WORKSHOPS

I regularly give tutorials on processor architectures and hardware security. Most recently I presented the second tutorial on Security of Quantum Computing Systems, as part of IEEE Quantum Week 2024. Among others, I have also previously given (virtual) tutorial on Securing Processor Architectures, as part of ASPLOS 2021, for example.

I have taught as part of the summer school on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, in July 14-20, 2019, in Fiuggi, Italy, where I gave lectures on Processor Architecture Security.

PROFESSIONAL SERVICE

I am an associate editor of ACM Transactions on Architecture and Code Optimization (TACO) and IEEE Computer Architecture Letters (CAL) and Springer's Journal of Hardware and Systems Security (JHSS)

I am founder and organizer of the Quantum Computer Cybersecurity Symposium held for the first time on Nov. 9, 2023.

I was co-organizer of the workshop on Hardware and Architectural Support for Security and Privacy (HASP) from 2015 until 2022. Since 2023 I am on steering committee of HASP.

I was a co-organizer of the inaugural New England Hardware Security (NEHWS) Day 2021 and NEHWS Day 2022. In 2023 I was publicity co-chair and web co-chair of NEHWS Day 2023.

I was publications chair for FCCM 2021.

I was a general co-chair of the 2021 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), held virtually in Sept. 2021.

I am program committee member (PC) or external review committee (ERC) member of recent and upcoming conferences: TIICS 2021, HPCA 2021, ASPLOS 2021, ISCA 2021 (ERC), HOST 2021, SPSL 2021, MICRO 2021, HPCA 2022, ISCA 2022, CHES 2022, HOST 2022, CCS 2022, ISCA 2023 (ERC).

Most recently I have served as session chair at following conferences and workshops: HPCA 2022 Session 2B: Security II, MICRO 2021 Session 3A: Security & Privacy I, ASPLOS 2021 Session 18: Security 1, HPCA 2021 Session 1A: Security Architectures, and Top Picks in Hardware and Embedded Security 2020 Session Two: Side-Channel Attacks on Machine Learning Hardware.

I advise and mentor undergraduate students, including through the 2021 Undergraduate Architecture Mentoring Workshop.

PROFESSIONAL DEVELOPMENT

I regularly participate in various professional development activities. My recent or upcoming activities include: participating in Actualizing Racial Equity throughout the Faculty Hiring Process workshop, April 29, 2022, participating in Leading Inclusive Lab Meetings workshop, Sept. 29, 2021, participating in Poorvu Center Learning Community: Teaching Science and Labs, Feb. to May, 2021, participating in Breaking the Habit of Bias workshop, Jan. 28, 2021,

EDUCATIONAL OUTREACH

I participate in educational outreach activities. My recent or upcoming activities include: presenting to high-school students as part of Yale Pathways Summer Scholars 2022, July 19, 2022.

TEACHING

EENG 428 / ENAS 968: Cloud Computing with FPGAs -- Intermediate level FPGA course focusing on the new cloud-based FPGA computing paradigm.

EENG 201: Introduction to Computer Engineering -- Introductory course for Computer Engineering.

EENG 467 / ENAS 967: Computer Organization and Architecture -- Intermediate level computer architecture course (the first Hennessy and Patterson book).

OPEN-SOURCE HARDWARE

My group regularly publishes hardware (and associated software) code for our projects under open-source licenses, mostly GPLv2 or newer.

To-date my group has published 16 projects totaling 179,056 lines of code. The hardware and software codes can be obtained from CASLAB's code page.
Data was updated on 2020-11-16. The data was computed using this script.

© Jakub Szefer, 2024